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News and information about the RISC-V instruction set architecture and its implementations, brought to you by .

Vrijeme pridruživanja: siječanj 2019.

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    Want to run Linux-on-LiteX-VexRiscV but don't have a FPGA board? Try installing on your computer and you can boot Linux on !

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    3. velj

    Video and slides of our talk at in the devroom are out: . We talked about , our open-source heterogeneous SoC platform. More info on the website: .

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    I just used for the first time yesterday while at and it was really exciting to be able to boot Linux on a simulated processor... plus its fast! Here is a talk from of about it:

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    My slides from : How to run Linux on with open hardware and open source FPGA tools

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  5. 2. velj
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  6. 1. velj

    Several presentations on at this year’s conference: Looking forward to seeing those talks when they’re posted online!

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  7. 1. velj

    Cf. chapter 5 “Hypervisor Extension, Version 0.5” of “The RISC-V Instruction Set Manual, Volume II: Privileged Architecture”* 📖 * Link goes to current draft as of this tweet; see for updated releases.

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  8. 1. velj

    RISC-V Standard Extension H (Hypervisor): Alistair Francis and Anup Patel’s 2019 RISC-V Summit presentation: 📺 Andrew Waterman’s 2017 RISC-V Workshop presentation: 📺 🔳

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  9. 31. sij
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  10. 29. sij

    Webinar recordings from : “Part I: An Introduction to the RISC-V Architecture” 📺 “Part II: SiFive’s 2 Series Core IP” 📺 “Part III: From a Custom 2 Series Core to ‘Hello World’ in 30 Minutes” 📺

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    29. sij

    Fun exercise in logic optimization; AES, AES inverse, and SM4 S-Boxes differ only in linear layers, so I added SM4 linear top and bottom layers to the Boyar-Peralta S-box. This is for the proposed super-lightweight RISC-V AES/SM4 instructions (parent dir).

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    29. sij

    Now you can not only build applications on your RISC-V host or VM but also use the fantastic cross-build capability of Go to compile your application to this new architecture. Just "GOOS=linux GOARCH=riscv64 go build ." And you are done. Fresh binaries.

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    26. stu 2019.

    RISCV visual emulator… PC top left, integer registers blow, memory on right. Memory potentially referenced by a register is color coded and linked. Registers, colors and links updated as I step through code. Please excuse WIP UI. SwiftUI layout is a bundle of fun.

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  14. 29. sij
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  15. 29. sij

    “RISC-V Cores and SoC Overview” — status of various cores and SoCs that endeavor to implement the RISC-V specification; includes information about supplier, links, spec, language, and license used: 👉 Repository: 📝 h/t

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  16. 29. sij
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  17. 29. sij

    RISC-V genealogy and collapsible tree: 👉 Dataset used by collapsible tree (JSON): 📎

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  18. 29. sij
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  19. proslijedio/la je Tweet
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    Joel Sing just finished landing the RISC-V port to the almost-out 1.14! It works! 🎉 (We'd made a special exception to let the stuff land during the freeze since it was mailed prior to the freeze, sufficiently isolated, and distros/people were waiting on it.)

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