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RISC-V.chip.haus proslijedio/la je Tweet
Want to run
@enjoy_digital Linux-on-LiteX-VexRiscV but don't have a FPGA board? Try installing@antmicro@RenodeIO on your computer and you can boot Linux on@RISC_V! https://github.com/litex-hub/linux-on-litex-vexriscv/pull/33#issuecomment-516329237 …pic.twitter.com/NUZh28fmKy
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RISC-V.chip.haus proslijedio/la je Tweet
Video and slides of our talk at
@fosdem in the@risc_v devroom are out: http://fosdem.org/2020/schedule/event/riscv_openesp/ …. We talked about#ESP, our open-source heterogeneous SoC platform. More info on the#ESP website: http://esp.cs.columbia.edu .@ColumbiaSld@ColumbiaCompSci@ColumbiaSEASpic.twitter.com/LA4sU4NF8m
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RISC-V.chip.haus proslijedio/la je TweetHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi
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RISC-V.chip.haus proslijedio/la je Tweet
My slides from
@FOSDEM: How to run Linux on@RISC_V with open hardware and open source FPGA tools https://github.com/pdp7/talks/blob/master/fosdem20.pdf …#FOSDEMpic.twitter.com/6RtBUmVi5j
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“How to Build a Trustworthy Free/Libre Linux Capable 64-bit RISC-V Computer” (Gabriel Somlo, 2019)
https://insights.sei.cmu.edu/sei_blog/2019/10/how-to-build-a-trustworthy-freelibre-linux-capable-64-bit-risc-v-computer.html …
http://www.contrib.andrew.cmu.edu/~somlo/BTCP/ Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
Several presentations on
@RISC_V at this year’s@FOSDEM conference: https://fosdem.org/2020/schedule/track/risc_v/ … Looking forward to seeing those talks when they’re posted online! https://www.youtube.com/user/fosdemtalks/playlists …#RISCVpic.twitter.com/OEEEEoGMfL
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Cf. chapter 5 “Hypervisor Extension, Version 0.5” of “The RISC-V Instruction Set Manual, Volume II: Privileged Architecture”*
https://github.com/riscv/riscv-isa-manual/releases/download/draft-20200125-8557cb3/riscv-privileged.pdf …
* Link goes to current draft as of this tweet; see https://github.com/riscv/riscv-isa-manual/releases … for updated releases.Prikaži ovu nitHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
RISC-V Standard Extension H (Hypervisor): Alistair Francis and Anup Patel’s 2019 RISC-V Summit presentation:
https://youtu.be/93C6CusxZ1Y
Andrew Waterman’s 2017 RISC-V Workshop presentation:
https://youtu.be/4JIvnWEs_pA
https://content.riscv.org/wp-content/uploads/2017/12/Tue0942-riscv-hypervisor-waterman.pdf …Prikaži ovu nitHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
RISC-V OS in Rust: System Calls (Stephen Marz, 2020 Jan.)
http://osblog.stephenmarz.com/ch7.html
https://youtu.be/6GW_jgkdGPw
/via https://news.ycombinator.com/item?id=22194896 …
#OSDev#RustLang#RISCVpic.twitter.com/m0pkR9LF81
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Webinar recordings from
@SiFive: “Part I: An Introduction to the RISC-V Architecture”
https://youtu.be/m8DqCTogb8w
“Part II: SiFive’s 2 Series Core IP”
https://youtu.be/P3MmLPgD8KI
“Part III: From a Custom 2 Series Core to ‘Hello World’ in 30 Minutes”
https://youtu.be/dwKnqE3beWI Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
RISC-V.chip.haus proslijedio/la je Tweet
Fun exercise in logic optimization; AES, AES inverse, and SM4 S-Boxes differ only in linear layers, so I added SM4 linear top and bottom layers to the Boyar-Peralta S-box. https://github.com/mjosaarinen/lwaes_isa/blob/master/hdl/sboxes.v … This is for the proposed super-lightweight RISC-V AES/SM4 instructions (parent dir).
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RISC-V.chip.haus proslijedio/la je TweetHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi
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RISC-V.chip.haus proslijedio/la je Tweet
RISCV visual emulator… PC top left, integer registers blow, memory on right. Memory potentially referenced by a register is color coded and linked. Registers, colors and links updated as I step through code. Please excuse WIP UI. SwiftUI layout is a bundle of fun.pic.twitter.com/XJPMUFWCZT
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“PULP: Open Hardware at the Edge of the IoT” (Davide Rossi, HiPEAC WRC 2020)
Slides https://pulp-platform.org/docs/hipeac/2020/PULP_WRC_2020.pdf …
Info https://web.fe.up.pt/~specs/events/wrc2020/index.php?page=keynotes#presentation_rossi …
/via https://pulp-platform.org/conferences.html … @pulp_platformPrikaži ovu nitHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
“RISC-V Cores and SoC Overview” — status of various cores and SoCs that endeavor to implement the RISC-V specification; includes information about supplier, links, spec, language, and license used:
https://riscv.org/risc-v-cores/
Repository:
https://github.com/riscv/riscv-cores-list …
h/t @pdp7pic.twitter.com/yP9i6HhM82
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Report: “RISC-V Genealogy” (Tony Chen & David Patterson, 2016)
https://content.riscv.org/wp-content/uploads/2016/02/EECS-2016-6.pdf …
Poster: “RISC-V Instruction Set Lineage”
https://content.riscv.org/wp-content/uploads/2016/02/RISC-V-Instruction-Lineage-Poster-v6.pdf …
#RISCV#ComputingHistorypic.twitter.com/px1Gkcnrfh
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RISC-V genealogy and collapsible tree:
https://riscv.org/risc-v-genealogy/ …
Dataset used by collapsible tree (JSON):
https://riscv.org/riscv.json
#RISCV#ComputingHistorypic.twitter.com/SG53Njkqam
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RISC-V.chip.haus proslijedio/la je Tweet
RISC-V and open source chip designhttps://www.slideshare.net/DrewFustini/riscv-and-open-source-chip-design …
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RISC-V.chip.haus proslijedio/la je Tweet
Joel Sing just finished landing the RISC-V port to the almost-out
#golang 1.14! It works!
(We'd made a special exception to let the #riscv stuff land during the freeze since it was mailed prior to the freeze, sufficiently isolated, and distros/people were waiting on it.)pic.twitter.com/slUMO5brgH
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