Do Intel's TSX transaction instructions allow you to do something similar? I assume that an interrupt would abort the transaction.
A quirk of the x86 architecture allows userland processes to observe when they've been interrupted by an interrupt handler: https://lackingrhoticity.blogspot.com/2018/01/observing-interrupts-from-userland-on-x86.html …
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If the interrupt doesn't evict or otherwise affect L1 cache lines involved in the transaction, I think it's indeterminate whether it will abort.
End of conversation
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