@Mark_Seaborn "rowhammer_test [...] only tests one channel" - fetches are always 128byte -> both channels are implicitly tested
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@Mark_Seaborn Adjacent Cache Line Prefetch Disable" in intel ref. manual and 2.2.5 Spatial Prefetcher in Intel Optimization Manual
@lavados Ah, OK. Initially I thought you meant the memory controller ran the channels in lockstep. Prefetch is at a different level.
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@Mark_Seaborn i observed the 128byte blockwise fetching when performing cache attacks, should have the same effect anyways, shouldnt it? -
@lavados Presumably, though I could imagine a memory controller might skip row-conflict prefetch requests (esp. on a laptop, to save energy) -
@Mark_Seaborn you're probably right... so far i only found flips on addresses with bit 7 set when hammering on adresses which have bit 7 set
End of conversation
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