Locuza

@Locuza_

Summaries and info pieces on Patreon / Zusammenfassungen und Infohäppchen auf Patreon:

youtube.com/channel/UCaFk_…
Joined February 2018
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  1. Pinned Tweet
    May 3

    This video includes what caught my eye after skimming through the open source driver patches for RDNA3. It goes over IP versions, some feature definitions, FSR code lines & more. Also on Patreon as a written text with images: 1/x

    1 reply . 13 retweets 65 likes
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  2. 12 hours ago

    What I noticed: - "True" 16 bit instructions - Dot8 includes 16-Bit accumulate (not only 32b) and RDNA3 supports now Brain Floating-Point 16. - Dual-Issue Wave32 could mean at the same time and not one after another, as for Wave64? - LDSBankCount is still 32 - Clustered Stores.

    2 replies . 1 retweet 19 likes
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  3. May 13

    It looks like the L3$ data array is no longer concentrated on one core side, but split in a left and right side per core, with the Ring Agent and Tags in the middle. Better seen in drawings.

    Replying to @Locuza_
    I'll bet on P L2$: 2M/core E L2$: 3M/cluster LLC: 4M/ring stop
    2 replies . 1 retweet 6 likes
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  4. May 13

    : gifted the world with an even better die shot! 😃 I remade and enhanced the previous annotations. Thanks to input, the cache interpretation changed. A short article in French can be found on :

    6 replies . 13 retweets 67 likes
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  5. May 11

    - No AVX512 FMA on Port 5 simply means that. Server chips have an extra set of EUs on Port 5 for twice the 512b FMA throughput, client chips don't have it and continue to not include it. - L3$ slice is claimed to be 3MB. 4/x

    Yes, Meteor lake keeps the same cache config as Raptor lake, 2M L2+3M L3 per P core. You can confirm it in this die shot. Next cache change maybe will appear in the arrow lake.
    1 retweet 6 likes
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  6. May 11

    So same situation as on Alder Lake in terms of hw support? Will the sw/os get an update to support asymmetric ISAs or will Intel again disable AVX512 on the large cores? Perhaps they will have a change of heart and allow AVX512, if E-Cores are disabled? 3/x

    2 replies . 1 retweet 10 likes
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  7. May 11

    Some comments. - Vec Regs seem to be similar to Golden Cove, so no shrinkage to 256b registers, still 512b. I would assume the hw still supports AVX512 via "port fusion", as GLC. Crestmont looks extremely similar to Gracemont, it likely still doesn't support AVX512. 2/x

    4 replies . 1 retweet 11 likes
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  8. May 11

    A Redwood Cove (P-Core) looks like an evolutionary Golden Cove (GLC). L2$ appears to be 2MB vs. 1.25MB on GLC. L3$ seems to be at least 2.5MB, but likely again 3MB? The Crestmont cluster seems to have 2-4MB shared L2$, not that clear to me. Die shot from:

    12 replies . 33 retweets 115 likes
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  9. Retweeted
    May 7
    Replying to

    => "HBM System and Architecture for AI applications", Rambus, Tutorial, VLSID 2022, Feb 26, 2022, (1:04:07) HBM => HBM2/2E => HBM3 HBM ECC capabilities Interposer Design: HBM3 The HBM3 Roadmap Is Just Getting Started, Apr 6 HBM3 RAS

    1 reply . 1 retweet 4 likes
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  10. Retweeted
    May 9

    Open jobs at dropped significantly from over 3100 in march to now 2700. had a big jump at the beginning of 2022 and is seeking over 6000.

    3 replies . 7 retweets 52 likes
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  11. May 5

    SXM1 w/ GP100 = 140 x 78 mm SXM2 w/ GV100 = 140 x 78 mm SXM4 w/ GA100 = 140 x 78 mm ? SXM5 w/ GH100 = 150 x 80 mm ? If 150 x 80, I get ~822.88 mm² for the H100 die size. Official size: 814 mm² (w/o scribe lines, so it would check out). Package size would be 55 mm x 58 mm.

    1 reply . 1 retweet 29 likes
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  12. Retweeted
    May 4

    Frontier's MI250X is higher clocked as compared to those for the "regular market". They're clocked at 1.88 GHz for a total of 53.0 TFLOPs FP64 per OAM. For comparison, the regular MI250X is clocked at 1.7 GHz for a total of 47.9 TFLOPs FP64 per OAM.

    1 reply . 10 retweets 46 likes
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  13. May 4

    - Legacy geometry pipeline support gone, only Next Generation Geometry (NGG) now. - Geometry stream output unimplemented for now - Offchip buffering is handled per Shader Engine - Instruction cache line is now 128 bytes not 64 anymore. 3/x

    3 replies . 4 retweets 38 likes
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  14. May 4

    - Removed Fragment and Color Mask (FMASK/CMASK) - No Multi-Sampling AA resolve inside the ROPs anymore, compute shader based (Hello R600, you were right all along) - Delta Color Compression (DCC) never needs decompression anymore, all formats are compatible. 2/x

    2 replies . 3 retweets 40 likes
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  15. May 4

    RDNA3 mesa commits: - New rasterizer control fields (Lightning accel.) - 6 Shader Engines for RDNA3 (8 in another place) - Variable Rate Shading (VRS) with 4 pixel supported, not only 2 - New Oreo🍪mode - Removed Enhanced Quality Anti-Aliasing EQAA 1/x

    4 replies . 21 retweets 126 likes
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  16. May 4

    Now it's "clear" what is behind PA_SC_BINNER_CNTL_2:

    3 replies . 1 retweet 16 likes
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  17. May 4

    Great findings from Frog. (YouTube need comment links, it's there) GFX11 patches for RadeonSI: The buffet is open!

    2 replies . 3 retweets 30 likes
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  18. Retweeted
    May 3

    Based on the info in this video, I decided to create 2 diagrams showing what each N31 design may look like Left is the familiar model, while the right has the new version Of course, this is 90% speculation (for instance, we don't even know if Model 2 has MCD, or if any have ICD)

    8 replies . 19 retweets 55 likes
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  19. May 3

    Just for fun, early diagrams for the Phoenix APU and Navi33. It's not clear yet if AMD has done major changes in regard to the 3D pipeline, cache config and scaling principles. So I just took RDNA2 blocks. RDNA3 only has one MEC, RDNA2 should now also use MES on Linux. 27/x

    6 likes
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  20. May 3

    VCN4 will be included inside RDNA3 chips. The codec query doesn't list AV1 encoding support, but PAL has an entry for AV1 encoding, noticed by in September. I fully expect VCN4 to offer AV1 encoding support. It should be updated later. 26/x

    1 reply . 4 likes
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  21. May 3

    RDNA3 sounds to be a real work of art. One thing which tampers my excitement a bit is the memory capacity. 8, 12 and 16 GB should be the launch configurations. Eugkra33 rightly pointed out on YT, that with clamshell it could be 16, 24 and 32. (No need for 4 GB G6 chips) 25/x

    1 reply . 5 likes
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