i.e. Producer isn't expected to read descriptors it writes to submission queue. Thus, no need to load their cache-lines to producer's L1/L2. Which also hurts Consumer latency on reading them. Thoughts? (2/3)
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Given Intel DDIO provides device with direct access to limited set of LLC ways, I would also expect to have a non-temporal store instruction that not only write directly to LLC, but can be hinted to write to DDIO-accessible LLC ways. E.g. To accelerate NIC/NVMe submissions. (3/3)
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Maybe
@0xdbug has an idea? -
Sorry for late here. I m not from Si/design team. It'll violate cache inclusion principle that Intel CPUs follow (data in LLC implies that data will be in MLC/L1). Will require to re-design cache coherency policies (LLC and main memory have to coherent as well + inclusion rules).
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