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That is assuming there are backwards compatibility reasons why you have to keep supporting 4k pages in "compatibility" mode, etc. - I can't honestly see there being a point to 4k pages for the normal case of modern apps that all use literally gigabytes of memory?
Also, paging is kind of for chumps anyway? Like, the OS probably has to support it, but you don’t actually want to be doing it ever, so, probably should not design for that as a primary use case.
Writing 2MiB to NVMe should be microseconds, so we should instead be having this conversation about 1GiB pages
Oh also worth noting that each page size has its own l1 tlb (the large page tlbs are much smaller) so your actual access patterns matter.
Have you got any good ideas on what memory protection without paging might look like, e.g. maybe the ISA lets you specify whole ranges at a time instead of 4k chunks?
He's talking about VM paging, not the concept that there are pages. Jon is just saying that designing your paging system around the case where things page in/out is a bad idea, because that case should never happen in perf-centric scenarios (and I agree).
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