Now imagine using that memory controller enable a DRAM cache for the chipset IO. 
So for clarity: Rome large IO die = GF 14nm Matisse small IO die = GF 12nm X570 Chipset = Matisse IO die on GF 14nm That's right. The X570 chipset is the same floorplan as the Matisse IO die, but with diff chicken bits enabled/disabled. AMD has good reuse of chips
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thanks for confirming what
@Gordonung mumbled in a sleep deprived state during the live stream. -
Yeah, we we're all still pretty burned out from Computex. Took a while to get clarity on the differences during our prebriefings
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If they were the same silicon on the same process they would get economy of scale. But this way they only spare the design costs, which is why I find this setup baffling.
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Wonder if X570 chipset was built also using 7nm tsmc would it still require fan for cooling, though it would increase already high price of X570 mobos. May be next year, when 7nm is even more mature and cheaper to produce, they will do it for X670/Zen3
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Why wouldn't they just make the OI bigger and forget about the chipsets completely? maybe for zen 3?
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I guess at this point it's a matter of socket pin/wire count and locality. You want all those SATA and PCI-E wires away from the socket area that is already congested with RAM, PCI-E, and power delivery.
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Will the IO Chip moves to GF’s FD-SOI in the future? Or are they simply sticking to GF 14/12nm ?
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