@plgDavid seen this?
Alright! perfect6502 simulation hooked up to the chip visualization running though the visual6502 standard test program at one half-cycle per frame :D
https://floooh.github.io/oryol-sticky-tests/v6502r.html …
Time to start with the UI :)
(cc @pagetable )pic.twitter.com/jzoQPicdbb
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No but visual6502 (and the subcycle instruction simulation they provide) was a refenence in my 6502 core for edge cases. Really amazing work
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Not sure what I’m looking at, you have some more context?
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It's a transistor-level-simulated MOS 6502 8-bit CPU visualized in real-time. It's just a remix of existing projects though: Most importantly: http://visual6502.org/ , they did all the original hard work to reverse engineer the 6502 and build a software simulation...
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Wha- Why did I only just find out about this? I use a modified visual6502 sim to debug old chips, and have a to-do list of things to improve. Especially the speed. I'd love to collab with you on the refreshed version.pic.twitter.com/JUyi9LaaM9
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I've turned this into a "proper visual6502 remix" in the meantime with the chip simulation, logger and assembler integrated: https://floooh.github.io/visual6502remix/ … Source is here: https://github.com/floooh/v6502r Need to write build instructions etc, they're similar to:https://github.com/floooh/chips-test …
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Beautiful.
Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi
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Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi
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Love it !
Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi
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I love this the most.
Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi
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