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btw i would not expect 10x better than competition (even x86) improvement in any risc-v SoC, while it may be a libre ISA, the ISA shares several design flaws with MIPS (itself derived from original Berkeley RISC architecture).
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the advantages to risc-v are political (it's a libre ISA), not technical. it is possible to get good performance out of risc-v, but microarchitectural optimization will be a challenge due to the lack of condition codes
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“As A2 was designed in 2010, A2I and A2O are not compliant with the Power ISA 3.0 or 3.1 which is mandatory for OpenPOWER cores. It is IBM's wish for the cores to be updated so they comply with the newer version of the ISA.” that’s the gotcha.
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That doesn't seem like much of a gotcha. Those core designs are Apache 2 licensed with the patent grant extended to cover physical hardware. Can do whatever you want with those including updating them to support the modern ISA.
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