this still hasn't actually been released yet:
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btw i would not expect 10x better than competition (even x86) improvement in any risc-v SoC, while it may be a libre ISA, the ISA shares several design flaws with MIPS (itself derived from original Berkeley RISC architecture).
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the advantages to risc-v are political (it's a libre ISA), not technical. it is possible to get good performance out of risc-v, but microarchitectural optimization will be a challenge due to the lack of condition codes
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OpenPOWER is a fully open source ISA without those weird design decisions / limitations. There are multiple open source core designs based on it including en.wikipedia.org/wiki/IBM_A2.
ARMv8 ISA is somewhat cleaner since they did a clean break from ARMv7 and cleaned it up a lot.
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i’m not so sure on that. if somebody started making OpenPOWER chips that were competitive to IBM’s offerings i’m sure they would find some litigation vector.
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“As A2 was designed in 2010, A2I and A2O are not compliant with the Power ISA 3.0 or 3.1 which is mandatory for OpenPOWER cores. It is IBM's wish for the cores to be updated so they comply with the newer version of the ISA.”
that’s the gotcha.
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That doesn't seem like much of a gotcha. Those core designs are Apache 2 licensed with the patent grant extended to cover physical hardware. Can do whatever you want with those including updating them to support the modern ISA.
One of the few complaints that I've seen about the ISA from the en.wikipedia.org/wiki/Libre-SOC project is that the vector instructions are defined as mandatory so they want to define a new ABI for Linux distributions to use without those since it would be the majority of the complexity.
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groups.google.com/g/linux.debian
I don't think not having the vector instructions (VSX) is that big of a deal as a starting point. If they made VSX optional then it wouldn't be hard for others to catch up and implement the latest revision of the architecture again.
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