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Prikvačeni tweet
Microbenchmarking the store and load buffer sizes on my zen2 machine as a follow up to the thread over at https://twitter.com/trav_downs/status/1187926177563979777 …. Tests written by
@trav_downs show that the SB size seems to be 48, confirming what is already on his blog. LB size is 116, ~60% increase over zen1.pic.twitter.com/SP8E1hEeOO
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Hey HPC twitter! It has been a great time helping build this team. We have some incredible students who are going to be representing
@GeorgiaTech at the@SCCompSC. Reach out if you would like to help us get to#SC20!https://twitter.com/hpcgarage/status/1225177597815992328 …
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Vijay proslijedio/la je Tweet
Our Interview with Andrew Feldman CEO of Cerebras Systems on making a revolutionary new AI platform https://www.servethehome.com/our-interview-with-andrew-feldman-ceo-of-cerebras-systems/ …
@CerebrasSystems#AI#WaferScalepic.twitter.com/9p4nYKtlDo
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Vijay proslijedio/la je Tweet
I promised at
#SC19 that we would open-source SYCL for NVIDIA GPUs using Intel's DPC++ SYCL compiler and here it is. It's a work-in-progress, but being actively developed. You can try it out today enabling DPC++ SYCL on NVIDIA GPUs without using OpenCL. You might like hipSYCL toohttps://twitter.com/codeplaysoft/status/1224309376548319232 …
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Vijay proslijedio/la je Tweet
#Intel closes the door on#Nervana, focuses instead on#Havana in a gutsy shift in#AI strategy. #https://lnkd.in/eYVQh9PHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
Vijay proslijedio/la je Tweet
Students can get a free trip to
@cppnow if accepted into the student/volunteer program! Apply now: http://cppnow.org/announcements/2019/12/2020-call-for-student-volunteers/ … Please retweet.Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
Vijay proslijedio/la je Tweet
New post, "Not All Zeros Created Equal": https://travisdowns.github.io/blog/2020/01/20/zero.html … A twisted tale about the fragility of high level type-traits based optimization.
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Vijay proslijedio/la je Tweet
Heard about
#Intel AVX-512 performance transitions party from the the cool kid down the block, but not sure if your parents will let you go? I'll go there so you don't have to: https://travisdowns.github.io/blog/2020/01/17/avxfreq1.html … Includes run-on sentences weighed down by up to three footnotes each.Prikaži ovu nitHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
For those who have a zen system, you do not have to build and run this entire kernel! Just go into the trunk/tools/perf directory and run make there. That should be it
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If you are testing, and want to refer to the PPR manuals from AMD, they can be found at https://www.amd.com/en/support/tech-docs …. I am using the latest versions for F17h Model 01/08/11/18 (Zen1) and Model 71h (Zen2)
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Current mainline does not have support for Zen2 counter even almost six months after launch. The PPR has some weirdness as well that I have noted at the end of the gist. PMCs 0x86,0x87,0xC7,0xD2 are not listed in latest zen1/zen2 PPR but are measurable?? What do???
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To help you the best I can with testing, I have made a list of diffs between counters here https://gist.github.com/thakkarV/5b12ca5fd7488eb2c42e451e40bdd5f3 …. Note the ones I have marked with @.high and @.critical annotations. These are ones I need most help with. e.g. removed from zen2 PPR but still sample-able
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I need help! I just got done implementing PMC counter support in perf profiler for zen2. There are a lot of changes, and I wanted help from people who own a Zen1 or Zen2 based system to test if it actually works before I upstream it. Please clonehttps://github.com/thakkarv/linux
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Winter break just started and ALL the HotChips31 sessions are up on YouTube!!! Time to get some popcorn...
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Vijay proslijedio/la je Tweet
Centaur lifts the veil on CNS, its next-generation high-performance x86 core for data center and edge computing. The new core also adds support for the AVX-512 extension.
#x86#16nm#CentaurTechnology#VIAhttps://fuse.wikichip.org/news/3099/centaur-unveils-its-new-server-class-x86-core-cns-adds-avx-512/ …Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
Vijay proslijedio/la je Tweet
On x86, the general purpose and SIMD registers get most of the press, product placement opportunities and essentially all of the hot after party invites. Let's shine a low level uarch light (what?) on their newly arrived sibling: the mask (k) registers.https://travisdowns.github.io/blog/2019/12/05/kreg-facts.html …
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Vijay proslijedio/la je Tweet
NEC refreshes its SX-Aurora Vector Engine accelerator cards with Type 10E models, adopts AMD processors, and outlines roadmap.
#SC19#VectorEngine#SXAurorahttps://fuse.wikichip.org/news/3073/nec-refreshes-sx-aurora-vector-engine-outlines-roadmap/ …Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
Vijay proslijedio/la je Tweet
An update on TSMC 5-nanometer process technology which is expected to ramp in early 2020.
#7nm#5nm#3nm#EUVhttps://fuse.wikichip.org/news/2879/tsmc-5-nanometer-update/ …Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
Test for mov xmm, xmm and mov ymm, ymm have an identical plot, sloping up at the ROB size. This is curious as well since the VPRF size is much smaller than ROB size. We get the same results for mov reg, reg+1.pic.twitter.com/qua4Qt0xse
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The plot thickens. Here are the results for mov reg, $0 and mov reg, $1. Moving constant 0 into a register has the same graph as zeroing and LB size test. This is different from moving 1 into a reg. Loop latency jumps for const 1 move at around 130-138 instruction depth.pic.twitter.com/3leY2MAaIN
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Zeroing idiom tests has the same graph as PRF test, indicating that zen 2 does not have a dedicated zero register, and if it does, rename does not recognize xor reg, reg as a zeroing idiom to just repoint it to the zero register.pic.twitter.com/5NhCOLxGtd
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