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And the fun begins. Using my tried and proven technique of instantiating UARTs on all IOs. Each UART sends it's number out it got in the generate block. Just probing now on the pins and the oscope serial decoder spits out the corresponding pin number 
pic.twitter.com/a2QaTgRXrh
Lunchtime, so far mapped out both GIG-E PHYs (Broadcom B50612D), all clocks (Two coming from each PHY:RX and TX clock, and a 25Mhz base clock from an oscillator) and the LED. After lunch I have to remove some nasty shorts, FPGA drives into the PHY TX lines. Chips getting 
hot
I think I have all short circuits/pin direction crash thingies sorted out now. And mapped out the SDRAM. Should be enough to start something serious on the module. Still on the to-do list is the SO-DIMM connector to FPGA mapping.pic.twitter.com/1KWigqT8s7
And done !
105 IO on the SO-DIMM connector
48 IO to SDRAM
27 IO to the GIG-E Phys
Some IO to 3 Analog Muxes
Clocks,JTAG and a LED
Rundown of the module specs:
ECP5U-45F, 64Mbit/32bit wide SDRAM,64Mbit Flash,2xGigE Phy. IOs to the outside are all on unbuffered 3.3V IO banks
That's a really neat technique!
It's a great use of the FPGA. Programmer: I want 178 UARTs. FPGA: Easy, done.
...out of all the hardware RE I've done, I've never thought of using a trick like this to map out FPGA pins. It's really clever, way to go.
You what?! That's cool!
It’s a cool trick, but how do you manage driving outputs onto pins driven elsewhere on the board? I used a similar hack which configured all pins to input except for one output, spotting pin changes (from poking pins with a signal gen) and sending out diffs on that one pin.
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