I still have to do the formal verification part, which is going to be challenging since @SpinalHDL apparently only supports clocked asserts.
But I have nothing better to do during Christmas anyway :D
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While watching @babbageboole implement a 6800 CPU in nMigen, I thought it looked very similar to @SpinalHDL, so I reimplemented it:
https://github.com/GuzTech/shdl6800 …pic.twitter.com/gOnHC06HCG
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I have just added the initial formal verification steps using the open-source
@symbiotic_eda tools and they pass \o/Prikaži ovu nit -
I've added processor flags and implemented several flag setting and branching instructions. Shown in the figure is a BRA instruction branching over a NOP instruction at address 0xA012.pic.twitter.com/s5TkrREvOs
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Added flag clearing instructions and formal verification to check flag manipulating instructions. Also fixed the branch instructions (I think) but couldn't formally verify yet because of a bug in
@SpinalHDL. This trace looks correct though (compared to the previous one).pic.twitter.com/DkPVomh61L
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I have manually worked around a bug that generates
$past() statements outside clocked always blocks, and fixed the branch instructions. Now they too pass formal verification \o/Prikaži ovu nit -
Implemented BNE and BEQ instructions and simplified the design a bit. And the nice thing is, is that because I formally verify the design, I can fearlessly refactor the implementation, knowing that the design will still work correctly.
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I have finished implementing my
@SpinalHDL version of@babbageboole's 6800 CPU as in part 3 of his series. It's tagged with "part_3", and I will use similar tags for the subsequent parts. https://github.com/GuzTech/shdl6800/tree/part_3 …Prikaži ovu nit -
Part 4 of the 6800 CPU implementation is done!
#FPGA https://github.com/GuzTech/shdl6800/tree/part_4 …Prikaži ovu nit -
Parts 5 and 6 of the 6800 CPU implementation are done!
#fpga https://github.com/GuzTech/shdl6800/tree/part_6 …Prikaži ovu nit -
I'm on a roll today. Part 7 of the 6800 CPU implementation is done!
#FPGA https://github.com/GuzTech/shdl6800/tree/part_7 …Prikaži ovu nit -
Part 8 of the 6800 CPU implementation is done!
#FPGA Some stats for Lattice HX8K:#cells (pre-PnR): 1881#cells (post-PnR): 1659 Max. frequency: 41.06 MHz So it uses a bit more than@babbageboole's implementation. Don't know about the frequency though. https://github.com/GuzTech/shdl6800/tree/part_8 …Prikaži ovu nit
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