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Prikvačeni tweet
While watching
@babbageboole implement a 6800 CPU in nMigen, I thought it looked very similar to@SpinalHDL, so I reimplemented it: https://github.com/GuzTech/shdl6800 …pic.twitter.com/gOnHC06HCG
Prikaži ovu nitHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
I'm going to present my arguments with as much confidence as I can muster, and the committee will have to worship it
https://twitter.com/GraceMallon3/status/1224332338009726977 …Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
天 Oğuz Meteer 天 proslijedio/la je Tweet
Okay -- looks like I'll be doing some course design on stream tomorrow (Feb 3); tentatively at 1PM MST. I'll be looking at options for translating my university-level Digital/FPGA design course into something open, accessible, & less-stuffy, and playing with
@esden's iCEbreaker!https://twitter.com/ktemkin/status/1223614085725487105 …Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
天 Oğuz Meteer 天 proslijedio/la je TweetHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi
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Also a big thank you to
@babbageboole for writing an nMigen tutorial:https://github.com/RobertBaruch/nmigen-tutorial …Prikaži ovu nitHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
While thinking of an optimization for an implementation in a future paper, I used
@M_Labs_Ltd nMigen and@symbiotic_eda formal verification tools to verify that both implementations are functionally equivalent \o/#FPGAPrikaži ovu nitHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
I must say it feels pretty liberating to have switched to
@ProtonMail and@ProtonVPN from gmail.Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
Now *this* is really cool!https://twitter.com/CasualEffects/status/1221883785987395584 …
Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi
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天 Oğuz Meteer 天 proslijedio/la je Tweet
Cows make milk. They milk themselves. Other cows check the milk (for free). Cows - get this - PAY THE FARMER to take the milk away. Then the farmer (you won't believe this, honestly) sells the milk *back to the cows.*
#academicpublishinghttps://twitter.com/DevilleSy/status/1216428583624855552 …Prikaži ovu nitHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
天 Oğuz Meteer 天 proslijedio/la je Tweet
this weekend I learned how to write an 1-bit
#deltasigma#DAC (#DSD#SACD) in#Verilog on an#FPGA, and the result is just stunning: https://www.youtube.com/watch?v=RsP_T7GeWYM … also#RISCV ;-)Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
I just bought Guilty Geary Xrd Rev.2 and of course I'm maining Baiken. I mean, look at that confident walk! How could I not main her?pic.twitter.com/wZBZltgIWu
Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi
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I'm proud that I have seen all the segments from this clip LMAOhttps://twitter.com/KyleKulinski/status/1215406209240567809 …
1:39Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
Part 8 of the 6800 CPU implementation is done!
#FPGA Some stats for Lattice HX8K:#cells (pre-PnR): 1881#cells (post-PnR): 1659 Max. frequency: 41.06 MHz So it uses a bit more than@babbageboole's implementation. Don't know about the frequency though. https://github.com/GuzTech/shdl6800/tree/part_8 …Prikaži ovu nitHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
I'm on a roll today. Part 7 of the 6800 CPU implementation is done!
#FPGA https://github.com/GuzTech/shdl6800/tree/part_7 …Prikaži ovu nitHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
Parts 5 and 6 of the 6800 CPU implementation are done!
#fpga https://github.com/GuzTech/shdl6800/tree/part_6 …Prikaži ovu nitHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
We're gonna keep you to it
https://twitter.com/wren6991/status/1214405736471683072 …Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
So I forgot to place the position of end_instr_handler, which caused cycle to not be reset to 0. The result is a working core
pic.twitter.com/VlZVHx117WPrikaži ovu nitHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
So the formal asserts that are checked is that the "JMP ext" instruction correctly jumps to the correct location. This happens, but the CPU then hangs, but there is no assert that checks if progress is made *after* the JMP.
@babbageboole Progress assertions seem important :)Prikaži ovu nitHvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi -
天 Oğuz Meteer 天 proslijedio/la je Tweet
Pushed Rudi-RV32I to
@Github - A#RISCV RV32I processor. Runs at 70MHz on@XilinxInc Artix-7#FPGA (e.g.@DigilentInc Basys3) No pipelining and runs one instruction per cycle (unless stalled during a LW/LH/LB) - Needs 573 LUTs, 30 FFs for CPU.https://github.com/hamsternz/Rudi-RV32I …Hvala. Twitter će to iskoristiti za poboljšanje vaše vremenske crte. PoništiPoništi
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Philosopher dude, c.1770: Here are some Thoughts I had in the Bath. They constitute Universal & Self-Evident Laws of Nature. FIGHT ME.