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@BitlogIT

PhD candidate | Writer at the BitLog technology blog | connoisseur | Mastodon: @ometeer@mastodon.social | IRC: GuzTech

Vrijeme pridruživanja: prosinac 2016.

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  1. Prikvačeni tweet
    25. pro 2019.

    While watching implement a 6800 CPU in nMigen, I thought it looked very similar to , so I reimplemented it:

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  2. 3. velj

    I'm going to present my arguments with as much confidence as I can muster, and the committee will have to worship it 🤣

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  3. proslijedio/la je Tweet
    3. velj

    Okay -- looks like I'll be doing some course design on stream tomorrow (Feb 3); tentatively at 1PM MST. I'll be looking at options for translating my university-level Digital/FPGA design course into something open, accessible, & less-stuffy, and playing with 's iCEbreaker!

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  4. proslijedio/la je Tweet
    30. sij

    Shamelessly stolen

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  5. 30. sij

    Also a big thank you to for writing an nMigen tutorial:

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  6. 30. sij

    While thinking of an optimization for an implementation in a future paper, I used nMigen and formal verification tools to verify that both implementations are functionally equivalent \o/

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  7. 29. sij

    I must say it feels pretty liberating to have switched to and from gmail.

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  8. 27. sij
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  9. 27. sij

    I don't watch basketball, but when I was in the US in 2010, we went to a Lakers game. They were losing until they put in the game. He single-handedly overturned the score, and it got even ME hype! R.I.P. the GOAT

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  10. proslijedio/la je Tweet
    16. sij

    Cows make milk. They milk themselves. Other cows check the milk (for free). Cows - get this - PAY THE FARMER to take the milk away. Then the farmer (you won't believe this, honestly) sells the milk *back to the cows.*

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  11. proslijedio/la je Tweet
    12. sij

    this weekend I learned how to write an 1-bit ( ) in on an , and the result is just stunning: also ;-)

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  12. 11. sij

    I just bought Guilty Geary Xrd Rev.2 and of course I'm maining Baiken. I mean, look at that confident walk! How could I not main her?

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  13. 10. sij
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  14. 10. sij

    I'm proud that I have seen all the segments from this clip LMAO

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  15. 9. sij

    Part 8 of the 6800 CPU implementation is done! Some stats for Lattice HX8K: (pre-PnR): 1881 (post-PnR): 1659 Max. frequency: 41.06 MHz So it uses a bit more than 's implementation. Don't know about the frequency though.

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  16. 9. sij

    I'm on a roll today. Part 7 of the 6800 CPU implementation is done!

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  17. 9. sij

    Parts 5 and 6 of the 6800 CPU implementation are done!

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  18. 7. sij
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  19. 7. sij

    So I forgot to place the position of end_instr_handler, which caused cycle to not be reset to 0. The result is a working core 👍

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  20. 7. sij

    So the formal asserts that are checked is that the "JMP ext" instruction correctly jumps to the correct location. This happens, but the CPU then hangs, but there is no assert that checks if progress is made *after* the JMP. Progress assertions seem important :)

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  21. proslijedio/la je Tweet
    4. sij

    Pushed Rudi-RV32I to - A RV32I processor. Runs at 70MHz on Artix-7 (e.g. Basys3) No pipelining and runs one instruction per cycle (unless stalled during a LW/LH/LB) - Needs 573 LUTs, 30 FFs for CPU.

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