FWIW, C's volatile does *not* guarantee to force anything on the CPU level. It forces the *compiler* to move things from registers back to memory, but the CPU caching can delay writing back (It's a bit different on MSVC)https://twitter.com/omegataupodcast/status/1074663628643753985 …
Well, it'll be a normal store, without accompanying barriers or such. So the precise model of coherency one will get will depend on hardware. The context was that the podcast at least strongly implied that a C volatile store would write through the cache.