Most HSMs that matter have long ago adopted an “FPGA in a tamper-proof metal box” approach, but that is not a silver bullet
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Replying to @0xABD @AndreaBarisani
PKI key generation requires power, entropy, and trusted isolation well suited for “FPGA in a safe” model, as prescribed by authorities
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Replying to @0xABD @AndreaBarisani
Smartcards were never that good at PRNG nor asymmetric key generation, but that does not mean they have to be abandoned in favor of SoC’s
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Replying to @0xABD @AndreaBarisani
Smartcards present a reduced attack surface and formidable countermeasures against SCA and FI. SoC world is a dumpster fire in comparison
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Replying to @0xABD
I'd take a larger, but upgradable, attack surface over a smaller one which can only be replaced by physical means, any day of the year.
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Replying to @AndreaBarisani @0xABD
Also, side channels and FI are not a relevant threat in a wide variety of scenarios and can anyway be accounted for in SoC running firmware.
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Replying to @AndreaBarisani
Unfortunately, with the complexity of modern SoC’s __everything__ on the die can be a remote SCA or FI vector, see CLKSCREW, etc.
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Replying to @0xABD
With the correct code failsafes these can be detected and prevented or made extremely hard, in the safety world this is routine.
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Replying to @AndreaBarisani @0xABD
We demonstrated (@
#hwio17 & FDTC) a FI attack that yields code exec and entirely bypasses FI mitigations in SW, including failsafe checks.2 replies 0 retweets 3 likes -
Also random delays are equivalently ineffective. Any instruction can be a target, no point in protecting only some specific code portion.
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Complexity can be raised considerably for to make a successful attack highly complex and motivated with much reasonable effort imho.
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