The Infineon bug highlights a larger issue. Lower level crypto stack certifications failed to prevent varied classes of bugs. (1/4)
I'd take a larger, but upgradable, attack surface over a smaller one which can only be replaced by physical means, any day of the year.
-
-
Also, side channels and FI are not a relevant threat in a wide variety of scenarios and can anyway be accounted for in SoC running firmware.
-
Unfortunately, with the complexity of modern SoC’s __everything__ on the die can be a remote SCA or FI vector, see CLKSCREW, etc.
-
With the correct code failsafes these can be detected and prevented or made extremely hard, in the safety world this is routine.
-
We demonstrated (@
#hwio17 & FDTC) a FI attack that yields code exec and entirely bypasses FI mitigations in SW, including failsafe checks. -
I am well aware of your (spectacular) research :), but I would still argue that for most use cases a smartcard is not intrinsically better.
-
On that point (& many others) I agree with you. It boils down on the threat model and the kind of attacks/attackers you're defending from.
End of conversation
New conversation -
Loading seems to be taking a while.
Twitter may be over capacity or experiencing a momentary hiccup. Try again or visit Twitter Status for more information.