The Infineon bug highlights a larger issue. Lower level crypto stack certifications failed to prevent varied classes of bugs. (1/4)
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Securing a modern SoC is not easy, no software can fix a TEE issue when a chip does not provide enough isolation on hardware level.
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Most HSMs that matter have long ago adopted an “FPGA in a tamper-proof metal box” approach, but that is not a silver bullet
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PKI key generation requires power, entropy, and trusted isolation well suited for “FPGA in a safe” model, as prescribed by authorities
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Smartcards were never that good at PRNG nor asymmetric key generation, but that does not mean they have to be abandoned in favor of SoC’s
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Smartcards present a reduced attack surface and formidable countermeasures against SCA and FI. SoC world is a dumpster fire in comparison
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I'd take a larger, but upgradable, attack surface over a smaller one which can only be replaced by physical means, any day of the year.
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Also, side channels and FI are not a relevant threat in a wide variety of scenarios and can anyway be accounted for in SoC running firmware.
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Unfortunately, with the complexity of modern SoC’s __everything__ on the die can be a remote SCA or FI vector, see CLKSCREW, etc.
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