Sounds reasonable, although I'd prefer the TZ memory to be discrete, outside of the SoC. We don't want TZ to evolve into IntelME, do we? ;)https://twitter.com/AndreaBarisani/status/790497935918235648 …
internal SoC RAM (example: 128Kb for the USB armory i.MX53)
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THX! If I read the correct specs, that should be an SRAM chip. If so, Rowhammer might be difficult indeed :)
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