#BadUSB alike in mobile Intel CPUs (Bay Trail, Core 4/5/6th gen)? https://www.google.com/search?q=%22USB+xHCI+may+Execute+a+Stale+Transfer+Request+Block%22&filter=0&gws_rd=cr&gbv=1 …pic.twitter.com/LkNVsgF57P
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and how would you manage to forge packets when you have no direct control over the PHY ?
the issues mentions problems with numerous endpoints connect/disconnect, that can be emulated
would you have as much power/possibility as if you had a usb PHY and you could bitbang at 60Mhz on it ?
no, I said "almost", however there is ULPI PHY access via indirect register which might come pretty close
nonetheless the scenario shown in the Intel errata doesn't feel to require absolute low level USB packet inject.
nah I was thinking that a next gen facedancer could be something like : ULPI PHYs + FPGA + FT601 (usb3)
I
low level tools and I'd welcome that (see our quest for soft Ethernet PHY) just don't feel it's required here
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