If you were starting from a clean slate, how would you make an "on-chip HSM" which wasn't as baroque (and broke) as SGX, TrustZone, etc?
I don't think it's even optional and it's always up to the SoC memory controller, and they all differ...
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completely agree with
@AndreaBarisani. Let's also add SW to the picture. E.g: EL3.1 wth crazy SMC handlrs -
Ptr checks performed in NWd, APIs allowing TAs map arbitrary memory, RWX memory maps..etc
End of conversation
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