If you were starting from a clean slate, how would you make an "on-chip HSM" which wasn't as baroque (and broke) as SGX, TrustZone, etc?
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this is up to TZ-aware memory controller and not core itself, this is the 2nd issue...only core TZ is standardized
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#iirc memory exclusion is present but optional, and never used indeed. -
I don't think it's even optional and it's always up to the SoC memory controller, and they all differ...
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completely agree with
@AndreaBarisani. Let's also add SW to the picture. E.g: EL3.1 wth crazy SMC handlrs -
Ptr checks performed in NWd, APIs allowing TAs map arbitrary memory, RWX memory maps..etc
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could it be helped by the ancient mechanism of “memory tagging”?
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it helps if you just understand pointer arithmetic...which you know when you do C you should do anyway, TZ or not
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Apple's TZ implementation is pretty damn good - interrupt based mailbox design and hardware filter.
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