No idea, the article alleges there was an extra chip that communicated with the BMC somehow, and interacted with RAM.
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Interconnection wise that would be a major feat, I guess a DMA bus master that interacts with memory and network controller is theoretically feasible though logistically it’s so hard (and invasive) to pull off...
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How about packaging it as an option ROM?
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Maybe but honestly isn’t it easier to just replace an existing component?
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Not really: SuperMicro boards are widely used, it is conceivable that different buyers flash the IPMI to their “internal standard”, especially large cloud providers. You need something which sits outside “expected stuff” but has access. Option ROM is a good choice: easy, loaded…
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at boot automatically during the compatibility phase of EFI or during legacy boot, has access to everything while the processor is in real mode pre-OS boot, etc. Not only, it is implemented even in EFI for non-x86 architectures.
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Let me offer and even more elegant design: your option ROM is actually against the BMC chip (an x86 in the latest ME, for example) which allows you to subvert the BMC in total transparency wrt the main processor.
End of conversation
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