Adam Taylor

@ATaylorCEngFIET

Professor of Embedded Systems, Chartered Engineer and Fellow of the IET, Experienced , , designer. Views My Own

Vrijeme pridruživanja: ožujak 2014.

Tweetovi

Blokirali ste korisnika/cu @ATaylorCEngFIET

Jeste li sigurni da želite vidjeti te tweetove? Time nećete deblokirati korisnika/cu @ATaylorCEngFIET

  1. Prikvačeni tweet
    6. sij 2019.

    Using devices for 1) AWS F1 2) Machine Learning 3) Image Processing - Parallel, MIPI, HDMI 4) Image Processing with HLS 5) IoT Frameworks 6) Robotics 7) Signal Analysis 8) SDSOC Acceleration 9) PetaLinux Check out my projects on

    Poništi
  2. 5. velj

    We get the best performance from our programmable logic design when we keep the data as close as possible. This week I am touching on the different memory types in Xilinx FPGA and especially Ultra RAM.

    Poništi
  3. proslijedio/la je Tweet
    4. velj

    Really happy to announce that you can now register for the upcoming Embedded Online Conference with , , , , , , , and many others.

    Poništi
  4. 2. velj

    A little Sunday morning fun with the RFSoC and the RFSoC Explorer which allows Matlab control, configuration and analysis of the RFSoC.

    Poništi
  5. 30. sij

    A little fun getting the Inc. Genesys ZU EG3 up and running with the PCAM and DisplayPort.

    Poništi
  6. 29. sij

    This week I am looking at the emulation flows in Vitis which enable us to develop our SW algorithm and optimize for acceleration.

    Poništi
  7. 27. sij

    Excited that my talk for PyCon in Pittsburgh on Python and FPGA has been accepted!

    Poništi
  8. proslijedio/la je Tweet
    23. sij

    Don't miss next Thursday's live, interactive workshop with ! Join us as we go step-by-step building a motor control project with the MiniZed. No FPGA experience required!

    Poništi
  9. 22. sij

    This week I am showing how to create a multi processor environment in Vitis with a MicroBlaze in the PL and the Arm A9 cores of the MicroZed #

    Poništi
  10. 20. sij

    Did you know according to the Mentor / Wilson group survey approximately 50% of FPGA are deployed in high reliability applications? If you are developing or thinking of developing a high reliability FPGA why not take a look at my developing FPGA for Miss…

    Poništi
  11. 15. sij

    This week I am demonstrating how to create a Vitis Acceleration platform for Zynq 7000 devices. This can be very useful for accelerating edge applications!

    Poništi
  12. 8. sij

    My first blog of 2020 looking at the RFSoC and the Avnet RFSoC Explorer.

    Poništi
  13. proslijedio/la je Tweet
    8. sij

    In his first MicroZed Chronicle of 2020, takes a closer look a prototyping RFSoC solutions with the RFSoC Explorer and :

    Poništi
  14. 2. sij

    2020 is 10 years since I wrote my first article for XCell Journal on FPGA design. Which looked at Mission Critical FPGA Design and was incredibly popular. 10 years later and I have written many articles, hundreds of blogs, with tens of millions of views…

    Poništi
  15. proslijedio/la je Tweet
    Odgovor korisnicima

    This has made my iteration time considerably faster, thanks for the advice! 🙂

    Poništi
  16. 30. pro 2019.

    Embedded Systems often need to be able to provide GUI for user interfacing. My latest Hackster project shows how we can get QT up and running on the Ultra96V1 and Ultra96V2.

    Poništi
  17. 26. pro 2019.

    Spent a little time this morning looking at how we can handle multi-processor embedded systems in Vitis. I thought a good example would be a MicroBlaze in the PL combined with a Arm A9 running in the PS.

    Poništi
  18. 23. pro 2019.

    My first Xilinx Vitis acceleration project for a Zynq 7000 device, running on the Avnet MicroZed.

    Poništi
  19. 20. pro 2019.

    Had a little pre-holidays fun today looking at the Avnet RFSoC Explorer. It is really impressive and allows you to get hands on with the RF ADC and DAC of the RFSoC from Matlab. Which means you can focus on the overall system performance.

    Poništi
  20. 18. pro 2019.

    Accelerating applications with Vitis on the Ultra96V2 platform. The first example on the custom platform we have been creating!

    Poništi
  21. 14. pro 2019.

    As it is the weekend I have been having a little fun with HLS and some fractals.

    Poništi

Čini se da učitavanje traje već neko vrijeme.

Twitter je možda preopterećen ili ima kratkotrajnih poteškoća u radu. Pokušajte ponovno ili potražite dodatne informacije u odjeljku Status Twittera.

    Možda bi vam se svidjelo i ovo:

    ·