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OasysDS

  1. Right Here, Right Now! RealTime Designer will be demo'd @DAC in Booth #530. More@http://tiny.cc/k0r4ew #49dac, #semip, #semieda 9:58 AM May 30th via web
  2. We made Gary Smith EDA’s WHAT TO SEE AT DAC 2012! See us @DAC Booth #530 to learn more. tiny.cc/efvpew #49dac, #semip, #semieda 8:49 AM May 22nd via web
  3. Peggy Aycinena interviews Joe Costello about Oasys for EDACafe@http://tiny.cc/5xhdew #49dac, #semip, #semieda 4:24 PM May 15th via web
  4. Russ Henke profiles Oasys on EDACafe@http://tiny.cc/b57xdw #49dac, #semip, #semieda 10:28 AM May 7th via web
  5. Amelia Dalton reports on our Intel Capital, Xilinx funding@EEJournal's Fish Fry. Listen@http://tiny.cc/sedxcw #49dac, #semip, #semeda 12:54 PM Apr 17th via web
  6. Power is everyone's business writes Oasys CEO Paul van Besouw on EETimes. Find it@http://tiny.cc/3aokcw #49dac, #semip, #semieda 4:19 PM Apr 10th via web
  7. Intel Capital, Xilinx invest in Oasys. Details@http://tiny.cc/m6zjcw #49dac, #semip, #semieda 7:38 AM Apr 10th via web
  8. Sandeep Bhatia shares his perspective w/EET readers on the evolution of DFT@http://tiny.cc/1vpkv #49dac, #semip, #semieda 11:52 AM Feb 16th via web
  9. Sandeep Bhatia writes about Design for test: a chip-level problem on Tech Design Forum@http://tiny.cc/zsl2x #49DAC, #semieda, #semip 11:15 AM Jan 25th via web
  10. RealTime Designer makes John Cooley's "Users name the Top 5 EDA Tools shown at DAC 2011!" More@http://tiny.cc/xxyxm #semieda, #semip, #49dac 9:03 AM Sep 29th, 2011 via web
  11. See Semiwiki's post on Oasys (Thx, Paul!)@http://tiny.cc/yzfeo & visit www.oasys-ds.com to watch our DAC video! #48DAC, #semieda, #semip, 9:46 AM Jul 21st, 2011 via web
  12. Bryon Moyer@EEJournal covers our DFT announcement, "Is That Any of Your Business?" Read it@http://tiny.cc/mwevo #48dac, #semip, #semieda 6:32 AM Jun 23rd, 2011 via web
  13. Paul van Besouw writes that power is a business problem in the 6/11 GSA Forum, p.30. Find it@http://tiny.cc/njtli #48dac, #semip, #semieda 6:52 AM Jun 20th, 2011 via web
  14. Power is a Chip-Level Problem writes Paul van Besouw for GABEonEDA's Assembling the Future@http://tiny.cc/af7uq #48DAC, #semieda, #semip 7:18 PM Jun 13th, 2011 via web
  15. Pondering the future of chip design? Check out what Paul van Besouw has to say on the subject@http://tiny.cc/z4b66 #48dac, #semieda, #semip 1:24 PM Jun 9th, 2011 via web
  16. We made John Cooley's Cheesy Must See List for DAC 2011@ http://tiny.cc/avg7s Stop by booth 2031 to find out why. #48DAC, #semieda, #semip 12:10 PM Jun 3rd, 2011 via web
  17. Visit our Booth@DAC#2836 for more on new DFT caps+chip-level power analysis/optimization. More@http://tiny.cc/j9mwg #48dac, #semieda, #semip 3:54 PM Jun 2nd, 2011 via web
  18. Don't miss John Cooley's Two stories Aart forgot to complete@http://tiny.cc/de54f #48DAC, #semip, #semieda 12:10 PM Apr 28th, 2011 via web
  19. Chip Synthesis adds chip-level power analysis, re-synthesize design from RTL w/power constraints. See http://tiny.cc/bpv2s #eda, #48dac 9:47 AM Feb 24th, 2011 via web
  20. Gary Meyers, former pres/CEO@Synplicity, joins our Board of Directors. More@http://tiny.cc/kmjh9 #eda, #semip, #48DAC 8:13 AM Feb 14th, 2011 via web