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GarySnA

  1. I'm giving a part 5/5 of an @DesignNews webinar series on System Level Testing and Debug today at 2:00 PM Eastern. designnews.com/lecture.asp?do…
  2. 10.3.9 Design each block with its own abort function that services just that block. #HwFw
  3. 5.8.4 Document the conditions and states that affect the variations of minimum, maximum, and typical times for each operation. #HwFw
  4. 3.3.5 Firmware: Work with the hardware engineer to find solutions to hardware/firmware interaction problems when they are discovered. #HwFw
  5. 11.1.3 Collaborate with firmware engineers on the design of test and debug hooks. #HwFw
  6. 3.2.5 Make sure that the firmware team is represented in reviews and signoffs of hardware checkpoints throughout the life cycle. #HwFw
  7. 4.5.4 Evaluate prior history, the existence of device drivers, and strong technical support when purchasing IP from a third-party. #HwFw
  8. 5.6.1 Display the register map in a horizontal format in the block's documentation. #HwFw
  9. 7.2.2 Provide data buffering, queuing, and chaining to maximize data throughput. #HwFw
  10. 4.6.1 Review the postmortem notes from the previous chip and apply appropriate changes to fix defects and add design enhancements. #HwFw
  11. 5.7.4 Assign the name, "Enable," to the register that controls which interrupts will propagate. #HwFw
  12. 11.2.4 Make counter and address registers readable even if they change rapidly. #HwFw
  13. 3.2.4 Make sure that the firmware team is represented in the chip design, the detailed block designs, and the testing plans. #HwFw
  14. 5.5.5 Document all interactions between registers. #HwFw
  15. 8.2.10 Avoid reusing bit positions of deleted bits in an existing register. #HwFw
  16. 5.4.9 Include a list of other documents to reference that may provide useful or necessary information for this block. #HwFw
  17. 9.6.3 Do not use an interrupt to indicate completion of firmware-launched hardware tasks that always complete instantaneously. #HwFw
  18. 3.2.6 Use co-development activities, such as virtual prototypes, FPGAs, co-simulation, and old hardware. #HwFw
  19. 4.5.2 Analyze each I/O block to ensure that it provides the proper buffer support for status, control, interrupts, errors, and debug. #HwFw
  20. 8.2.9 Avoid changing bit assignments from one version of the block to the next. #HwFw